Structure optimization design of CSP device based on Taguchi method

In order to improve the solder joint reliability of chip scale package (CSP) devices, based on the Taguchi method, the stress-strain distributions of the CSP device under thermal cycling are simulated by using the steady-state constitutive equations of Garofalo-Arrhenius and the finite element method. Considering the solder joint material, solder joint height, chip thickness and the thickness of the substrate four factors, using Taguchi method and orthogonal table L9(34) to arrange the experiment, the study found that the main influencing factors of solder joint reliability are the solder joint material and the height of solder joints. Optimized by Taguchi method, the best combination of materials is solder material Sn3.9Ag0.6Cu, solder joint height 0.29 mm, chip thickness 0.1 mm and substrate thickness 0.17 mm. Compared with the original design scheme, the optimal scheme reduces the creep strain energy density by 65.4% and the signal-to-noise ratio by 9.22 dB. The results show that the reliability of CSP solder joints is significantly improved.