Research on the fault diagnosis technology of connection failure belonging to the FPGA solder joint

This paper presents a model for detecting faults in FPGA(field programmable gate array) devices of BGA(ball grid array) type of packages using the method of SJ BIST(solder joint built-in self-test). It was theoretical analyzed in details, and simulated by simulation software-multisim. The DE2 hardware system of the Altera corporation was used to verify the model. The results showed that, compared with reference, the method of SJ BIST was analyzed in more detail, and the accurate impedance could be determined more accurately, and more exact information about health state of the FPGA solder joints can be obtained.