Research progress in low temperature bonding and patterning of metal nanomaterials
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摘要:
利用金属纳米材料的尺寸效应可显著降低连接温度,提高焊点可靠性,以银纳米焊膏为代表的金属纳米低温连接材料在第三代半导体为代表的功率芯片封装中充分验证并量产. 面向集成电路的先进封装需要图形化焊点,将功率芯片封装技术转移到先进封装中,需要同时满足低温键合和图形化键合的要求,极大地增加了技术难度. 文中首先剖析了金属纳米材料降低键合温度的基本科学原理,并进一步综述了不同纳米材料低温键合的研究现状,重点总结了可键合纳米材料的图形化方法,为先进封装中细节距、高精度、高效率的图形化低温键合提供技术参考.
Abstract:Utilizing the size effect of metal nanomaterials can significantly lower the bonding temperature and enhance the reliability of solder joints. Low temperature bonding metal nanomaterials, such as silver nano solder paste, have undergone extensive validation and mass production in the packaging of power devices, represented by third-generation semiconductors chips. However, when it comes to advanced packaging for integrated circuits that require patterned solder joints, the challenge lies in transferring power chip packaging technology to meet both low-temperature bonding and patterning bonding requirements, significantly increasing the technical complexity. This article begins by dissecting the fundamental scientific principles behind reducing bonding temperature through the utilization of metal nanomaterials. It then provides an extensive review of the current research status in low-temperature bonding with various nanomaterials. Finally, it focuses on summarizing patterning methods for bondable nanomaterials, offering technical insights for achieving precise spacing, high precision, and efficient graphical low-temperature bonding in advanced packaging.
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Keywords:
- advanced packaging /
- metal nanomaterials /
- low temperature bonding /
- patterning
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0. 序言
近年来随着新能源汽车、5G通讯和云计算等领域的发展,对计算芯片提出了更高计算能力的要求,功率半导体器件不同于其它类型半导体器件,能够耐受高电压、大电流,是实现电路转换与信号传输的核心,对电能的高效处理、传输等起到了关键的作用. 与此同时,高功率15的运行带来的导电导热需求,以及高温的使用环境,也对封装材料有着更高的需求[1-2]. 传统高温钎料,如金锡共晶合金(Au-Sn)、锡银共晶合金(Sn-Ag)等在烧结过程中会出现多种金属间化合物(intermetallic compounds,IMCs),使焊点可靠性下降,更重要的是上述钎料的热导率较低,限制了大功率器件的高温性能. 银是一种具有良好性能的材料,具有较高的导电导热性,但因其熔点过高,难以成为连接材料[3].
纳米银浆料是指尺寸大小在10 ~ 100 nm之间的银颗粒与多种有机物混合而成的一种连接材料[4],具有较高的比表面积,因此具有表面效应、体积效应、量子尺寸效应、宏观量子隧道效应和介电限域效应[5],由于极细的晶粒和大量处于晶界和晶粒缺陷中心的原子,纳米材料的物化性能与微米多晶材料有着巨大的差异,具有奇特的电学、热学和化学等多方面的性能,烧结后的浆料随着纳米银颗粒尺寸增大而熔点增高[6],能够在高温环境下进行使用,实现低温烧结高温服役的特殊烧结与应用形式,并且烧结后的浆料呈现优于其它高温钎料的导电导热性[7]. 纳米银浆料互连材料在低温互连、多级互连和大功率芯片互连等方向受到愈来愈多的关注,然而银的导热性能良好,块体银的导热率达429 W/(K·m),烧结后的纳米浆料在导热性能上却有显著降低.
针对于纳米银浆料的制备以及烧结后的导热性能变化已有许多人员进行了系统的研究. 刘彦立[8]通过仿真对比烧结后的纳米颗粒导热性能与纳米颗粒的孔隙率和孔隙形状等的关系,发现孔隙率是影响纳米导热性的主要因素;Wang等人通过不同烧结温度[9]、颗粒粒径[10]与烧结时间[11]的纳米浆料对比发现,通过不同尺寸的颗粒混合,提高烧结温度、增加烧结时间等方法能够有效降低孔隙率,从而提高纳米浆料的物理性能;Bai等人[12]通过对纳米浆料进行280 ℃烧结,热导率仅为238 W/(K·m),而银材料的热导率为429 W/(K·m),烧结过后的导热性能远没有达到预期程度;通过Li等人[10]的研究,采用双峰颗粒提高纳米浆料的致密度,也仅能使烧结后的纳米浆料热导率达到块体银的65%,造成烧结后的纳米浆料热导率远低于银材料的原因至今不够明确. 烧结过后颗粒烧结颈处的复杂结构可能对声子的传热有一定阻碍作用,从而降低了整体材料的热导率,但烧结过程中其微观结构尺寸较小,结构变化复杂,常规试验手段难以观察. 针对于纳米尺度原子的运动情况,已有学者[13-15]通过分子动力学仿真手段对其进行一定探索研究,通过仿真模拟指导实际的试验. 通过分子动力学仿真方法模拟纳米颗粒烧结过程中的结构变化,对烧结后的微观复杂结构计算其热导率,探究烧结颈处的缺陷结构是否对材料宏观性能造成一定影响.
1. 仿真方法
有大量学者针对纳米颗粒的熔化进行了分子动力学模拟,均取得了较为良好的成绩[13-15]. 分子动力学基于牛顿第二定律进行计算,将原子假设为实体小球,忽略原子的电子作用,考虑在相互作用下的运动情况,最终统计每一个原子的位移和速度从而计算其性能. 相比于第一性原理,分子动力学也是微观尺度的一种仿真方式,但是忽略了原子中电子的作用,对于一些只需考虑原子运动的仿真节约了大量算力,从而能够计算更大尺度上的仿真过程. 纳米银浆料的烧结过程是在高温的作用下原子扩散的行为,通过模拟原子的运动就可以较好地模拟其烧结过程,因此选择分子动力学进行仿真.
为了探究纳米颗粒烧结过程中的连接行为,建立两个直径为5 nm的纳米银颗粒的模型,为降低周期性边界条件中周围空间内颗粒对模拟的影响,设置颗粒到模拟环境边界的距离为20 nm,如图1所示,时间步长设置为0.001 ps,选择EAM势函数[16],周期性边界,在NPT系综下进行1 000 K烧结.
在金属材料中,传热作用主要依靠电子和声子的共同作用,其表达式[17]为
$$ \kappa = {\kappa _{\rm{e}}} + {\kappa _{\rm{p}}} $$ (1) 式中:κ为材料的热导率;κe为电子振动传热产生的热导率;κp为声子振动传热产生的热导率.根据Wiedeman-Franz定律,即
$$ \frac{{{\kappa _{\rm{e}}}}}{\sigma } = {{L}}T $$ (2) 式中:σ为材料的电导率;L为洛伦兹常数,取值2.45 × 10−8 W·Ω/K2;T为材料的温度. 声子对导热的贡献主要受晶格结构影响,目前还没有确定的公式能够进行计算,通过非平衡分子动力学方法计算纳米颗粒声子热导率的部分. 该方法通过给材料两端施加恒定热源与冷端,制造温度梯度,模拟得到材料内部在传热过程中的温度分布,根据傅里叶定律计算,即
$$ {\kappa _{{{\rm{p}}}} } = - \frac{Q}{{{\rm{d}}T/{\rm{d}}x}} $$ (3) 式中:dT/dx为传热方向上的温度梯度;Q为热流密度.
通过硝酸银与硼氢化钠溶液氧化还原反应合成纳米银颗粒,并在管式炉中进行烧结,将烧结过后的颗粒分别在泰思肯离子双束电镜TESCAN AMBER和透射电镜FEI Talos F200X下进行电子显微镜 (scanning electron microscope, SEM) 和透射电子显微镜 (transmission electron microscope,TEM)扫描,观察其微观结构.
2. 结果与讨论
2.1 势函数的验证
分子动力学模拟微观与介观尺度的原子运动情况,往往难以使用试验的手段对仿真的正确性进行验证,而仿真的结果差异主要来源于势函数的选择. 在仿真开始之前,首先对势函数的正确性进行验证,根据主要纳米颗粒的烧结规律以及微观结构的导热率问题,在验证过程中主要针对分子动力学能否较好的模拟出材料在导热性能上的尺寸效应,并进行验证.
建立横截面积为5 nm × 5 nm,导热长度Lz为10 ~ 35 nm,根据傅里叶定律与Wiedeman-Franz定律分别计算材料常温下在x方向上的热导率,并得到图2所示的长度与热导率关系曲线. 可以看到随长度增长,银材料的热导率不断增大,但增长趋势不断减缓,这一现象与文献[18]计算Al/Ni材料热导率以及文献[19]计算Si/Ge超晶格界面热阻过程中观察到的现象一致,表现了材料在导热性能上的尺寸效应.
根据材料的有效声子平均自由程和材料传热长度的关系以及量子力学中材料的热导率近似公式,可以推导出如下关系[20],即
$$ \frac{1}{{\kappa _{\text{p}}^{}}} = \frac{3}{{{{cv}}}}\left( {\frac{1}{{{{l}_\infty }}} + \frac{1}{{{L_{\text{z}}}}}} \right) $$ (4) 式中:v是声子速度; l∞为无限大系统内声子平均自由程, 为声子传热方向上长度. 式(4)表现了声子热导率的尺寸效应,将声子热导率的倒数与传热长度的倒数进行线性拟合,得到如图3所示的关系,通过线性拟合,表达式为
$$ \frac{1}{\kappa } = 0.002\;32 + \frac{{0.001\;11}}{{{{{L}}_{\text{z}}}}} $$ (5) 通过计算可以得到银材料在无限长传热方向上的热导率为431.03 W/(K·m),其与文献[21]中银材料热导率的试验值429 W/(K·m)的误差仅有0.5%.
使用嵌入原子势(embedded atom method, EAM)函数计算后的热导率与文献[20]的尺寸效应现象一致,计算得到的宏观热导率与试验值接近,证明所选择的势函数能够较为良好的完成仿真,并对研究纳米颗粒烧结后热导率变化情况具有一定的启示性作用.
2.2 晶格结构变化
将建模好颗粒在1 000 K下模拟烧结1 000 ps后进行降温,并在2 000 ps时观察降温后的稳定结构. 图4为烧结过程中0,25,250,500和1 000 ps时的颗粒形貌和位移云图. 从图中可以看出,随着烧结的进行,两个颗粒的原子都进行了相互扩散,颗粒形态由原来的双球状逐渐转变为椭球棒状.
图4原子模拟过程中运动的距离,颜色越偏向于红色,表明原子距离开始位置越远. 可以看出,在烧结过程中,颗粒表面的原子颜色更偏向于红色,说明在颗粒表面的原子进行了充分的扩散,都运动到了距初始位点较远的位置,而内部的原子位移距离很小,填充两个颗粒之间缝隙的原子主要来自于两边颗粒的表层原子.
进一步分析观察在烧结过程中纳米颗粒的晶格结构变化,将后处理文件在Ovito软件中进行晶格识别,根据每一帧图像中原子间配位数判断其满足的晶格结构,绿色代表规则排列的面心立方结构,红色表示密排六方结构,白色为未标定结构. 根据与试验结果比对分析,仿真软件识别出的片层状红色颗粒并不是密排六方结构,而是在烧结颈形成后在两侧形成的晶界,因其特有的配位结构被软件误认为密排六方结构. 白色为未标定的晶格结构,在模拟过程中存在两种情况,一种是在升温过程中由于扩散脱离晶格位点的原子,而另一种是在仿真开始,处于颗粒表面的原子因为没有满足面心立方的配位数,而被判定为未标定的晶格结构,最后为了观察到颗粒内部的晶格结构,对纳米颗粒进行剖面处理,如图5所示.
从图5中可以看出,在加热过程中,颗粒表面白色原子层变厚,原子吸收热能后转变为原子振动的动能,随机振动使原子失去了晶体的规则排列,表面的原子首先脱离了晶格位置,向表面能更小的位置进行扩散,填充到两个纳米颗粒中间的位置上,而颗粒内部仍保持较为完整的晶格结构,随着烧结过程的进行,在烧结颈处两边出现了晶界,纳米颗粒从原本的单一晶粒演变成多晶粒结构, 最后在冷却后形成面心立方的多晶结构,不同晶粒之间取向不同,晶界之间存在一定的夹角,而这一现象也在试验观察中得到了验证. 结合纳米颗粒烧结过程中原子的位移云图和晶格结构变化图,可以总结出形成烧结颈结构过程中主要的原子扩散方式是表面扩散.
图6是合成的纳米银颗粒分别在没有烧结前,200和250 ℃无压烧结1 h的SEM形貌. 从图中可以看出进行烧结后整体颗粒粒径变大,颗粒之间形成了明显的烧结颈结构,且随着烧结温度的提高,烧结颈的长度有明显的增长. 试验结果表明,在实际的烧结过程中存在两种颗粒连接的情况,对于不同尺寸的颗粒,大颗粒通过奥斯瓦尔德熟化现象融合小颗粒,颗粒本身粒径增长[22];对于尺寸相近的颗粒,其生长符合仿真情况,将产生烧结颈结构,通过一定时间的烧结,烧结颈的长度趋向于略小于颗粒直径.
图7是250 ℃无压烧结1 h选取几个尺寸相近的颗粒进行TEM观察的形貌,从图中可以看出有多个颗粒都进行了良好的冶金结合,其中还出现了颗粒堆叠,形成了莫尔条纹. 观察红色虚线内的两个颗粒,通过表面的原子扩散填充到颗粒相接触的地方形成烧结颈,填充后的原子呈规则排列,面间距为0.233 nm,通过计算为银的面心立方(111)晶面的面间距. 黄色箭头指向的多晶结构与仿真结果相对应,晶界之间的夹角一一对应,通过查阅文献[23],得出是银在纳米尺寸下的五重孪晶结构稳定状态,而烧结后的纳米颗粒内部同样出现了这一稳定结构.
图8为颗粒模拟烧结过程中烧结颈生长长度与时间关系,可以看到在烧结刚开始的阶段,烧结颈迅速增长,经过100 ps的烧结后,烧结颈已经具备一定长度,后续仍在增长,但增长的速度相较之前有所减少. 可以看出烧结颈的生长主要是在开始的阶段,原子迅速扩散,而当烧结颈结构生长到一定程度后,增速变缓,继续烧结将通过原子的滑移调整颗粒内部晶粒取向,最终形成多晶结构.
烧结颈生长规律这一现象也与粉末冶金中总结的烧结颈生长规律相似[15],即
$$ {\left( {\frac{X}{{{R}}}} \right)^{\text{m}}}{\text{ = }}\frac{{{H}}}{{{{{R}}^{{n}}}}}t $$ (6) 式中:X表示烧结颈长度(nm);m是与扩散机制有关的常数;R为颗粒半径(nm);H和n都是与扩散有关的常数. 烧结颈长度和时间成幂函数关系,拟合得出的公式为
$$ X^{8.076}=1.926 t$$ (7) 拟合得到m的数值为8.076,这与传统的各种扩散机制的数值均不同,说明在纳米尺寸下的扩散机制与宏观的扩散行为有所不同,具体的扩散机制还有待进一步探究.
2.3 晶格结构变化对导热的影响
为探究烧结时间对纳米颗粒的热导率的影响,分别选取烧结前、烧结中和烧结完成的纳米颗粒模型,针对于两个球心的截面处施加平行于烧结颈的平面恒定热源与冷端,平衡导热后输出其烧结颈处的温度梯度分布,结合热导率计算公式,计算得到纳米颗粒烧结结构的热导率.
图9为烧结0,25和2 000 ps颗粒内部温度分布及晶格结构剖面. 从图中可以看出,在烧结前,两个颗粒烧结颈位置处具有温度突变,证明没有形成烧结结构的两个颗粒之间具有较大热阻,而结构图中也可以看到两个颗粒连接处较窄小,并没有形成完整的晶格结构,对热量的传递有很大阻碍作用. 而在烧结过程中,两边仍有温度平台,此时具备一定的烧结颈结构,烧结颈处的原子对导热具有一定贡献,但是仍有很多没有规则排列的白色原子,其对热量的传递仍有阻碍作用;当完全烧结后,热量传递过程中形成温度梯度,证明此时热量能够稳定地从热源传递到冷端,两个颗粒之间热阻显著降低. 烧结完全后计算得到纳米颗粒烧结颈处的热导率为410.73 W/(K·m),与相同尺寸下规则排列的银材料的热导率仍有一定差距,其可能的原因是在烧结颈处形成了不同的晶格结构,阻碍了声子的热扩散运动,从而在一定程度上降低了热导率. 仿真中烧结后的两个纳米银颗粒烧结颈处的热导率相较于块体银下降了4.42%,然而文献[10]表征试验中纳米银浆料烧结后热导率出现大幅下降,甚至下降到了块体银热导率的65%,相较之下,烧结颈处的微观结构对热导率的阻碍作用并不明显.
3. 结论
(1) 颗粒在烧结过程中表面的原子会扩散到颗粒连接的地方,形成面心立方结构的烧结颈,烧结后的浆料内部会倾向于形成五重孪晶的稳定多晶结构.
(2) 烧结颈的生长主要在初期阶段,烧结颈生长长度与时间关系满足幂函数关系,拟合公式X 8.076=1.926t,符合烧结颈生长经验公式的规律.
(3) 通过仿真3个时间节点的温度分布,发现烧结颈处的微观结构的确一定程度阻碍了热量的传递,热导率下降到410.73 W/(K·m),相较于纯银块体下降了4.42%. 此外还发现通过完整的烧结可以降低纳米银颗粒之间的热阻.
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图 1 3种扩散过程中的空位扩散机制[17]
Figure 1. Vacancy diffusion mechanism in three diffusion processes. (a) between two nanoparticles; (b) between nanoparticle and substrate; (c) between two substrates
图 2 两个等粒径纳米颗粒的扩散模型[21]
Figure 2. Diffusion model of two equal size nanoparticles
图 3 离散元模型模拟40 000个颗粒烧结(红色部分代表晶界)[33]
Figure 3. Discrete element model simulation of 40,000 particles sintering (red part represents grain boundaries)
图 5 纳米颗粒焊膏烧结工艺过程[41]
Figure 5. Sintering process of nanoparticle solder paste
图 6 三模银膏和纳米银膏在180 °C烧结后的横截面SEM图像[42]
Figure 6. SEM images of cross-sectional die attachment using trimodal-Ag paste and nano-Ag paste sintered at 180 °C. (a) trimodal-Ag paste; (b) nano-Ag paste
图 8 银纳米线膜用于低温键合[49]
Figure 8. Silver nanowire film for low temperature bonding. (a) physical appearance; (b) microscopic morphology; (c) SEM image sintered at 250 ℃; (d) SEM image sintered at 300 ℃
图 9 铜纳米线烧结[50]
Figure 9. Sintering of copper nano-wire. (a) Cu nanowires prepared on Cu core; (b) cross-section image
图 10 混合纳米焊膏用于低温键合[36]
Figure 10. Hybrid nano solder paste for low temperature bonding. (a) a schematic of mixed paste; (b) SEM image of mixed paste: (c) SEM image sintered at 200 ℃ for 30 min in air; (d) the cross-section of joint sintered by mixed pastes
图 11 烧结银片与银颗粒的TEM图像[52]
Figure 11. TEM image of sintered silver flake and silver particles. (a) TEM image of sintered Ag flakes; (b) the local magnified view; (c) TEM image of sintered Ag particles; (d) the local magnified view
图 12 不同微纳米银焊膏在200 ℃镀银铜衬底上烧结60 min样品横截面的SEM形貌[54]
Figure 12. Cross sections SEM images of different micro/nano silver paste sintered on Ag-coated Cu substrates for 60 min at 200 ℃. (a) Ag micrometer-particle paste; (b) Ag nanoparticle paste; (c) Ag micrometer-flake paste; (d) Ag nano-thick-flake paste
图 13 银纳米片烧结机理示意图[37]
Figure 13. Schematic diagram of sintering mechanism of silver nanoflake
图 14 不同银焊膏形貌及烧结后接头截面微观结构[57]
Figure 14. Different silver paste morphology and sintered joint cross-section microstructure. (a) silver paste morphology; (b) cross-section microstructure of sintered joint
图 15 应用Au-Ag脱合金法制备金纳米多孔骨架[38]
Figure 15. Gold Nano-porous skeleton was prepared by the Au-Ag dealloying method. (a) sponge bump of 50 μm diameter; (b) nanostructure with different etch conditions; (c) SEM image of sintered joint at 200 ℃-10 MPa; (d) magnified SEM view on densification bonding zone
图 16 脱合金法制备的1 μm 金纳米多孔骨架阵列[59]
Figure 16. 1 μm Au nano-porous skeleton array prepared by dealloying method. (a) SEM image of bump array; (b) cross-section SEM image of bumps
图 17 Cu-Zn脱合金制备纳米多孔骨架用于低温键合[10]
Figure 17. Nano-porous skeleton prepared by Cu-Zn dealloying for low temperature bonding.(a) 10 μm dealloyed nanoporous-Cu bump; (b) FIB cross-section image of nanoporous-Cu bump; (c) substrate-side shear interfaces
图 19 采用压电喷墨打印制备的发光二极管阵列[66]
Figure 19. Light-emitting diode arrays prepared by piezoelectric inkjet printing. (a) 25 μm;(b) 38 μm
图 21 浸蘸转移过程示意图[71]
Figure 21. Schematic of the dip transfer process
图 22 不同直径及节距铜柱的润湿情况(虚线代表设计的铜柱尺寸及节距,不同颜色柱状图代表实际的润湿直径分布)[71]
Figure 22. Wetting conditions of copper pillar with different diameters and pitch (dashed lines represent the designed copper pillar size and pitch, and different color bars represent the actual wetting diameter distribution). (a) wetting diameters of different copper pillars; (b) optical images of different samples
图 23 图形化沉积微米银焊点工艺过程[75]
Figure 23. Patterning deposition of micron silver bumps process. (a) laser machined stainless steel mask; (b) mask pasted to DBC substrate; (c) PLD patterning deposition; (d) deposited micron silver bumps
图 24 图形化沉积银纳米颗粒凸点用于低温键合[76]
Figure 24. Patterned deposition of silver nanoparticles bumps for low temperature bonding. (a) 100 μm diameter patterned bumps prepared by deposition with PI mask; (b) cross-section image after bonding; (c) fracture interface of sintered bumps; (d) magnified SEM image of the dense part
图 25 磁控溅射制备铜纳米颗粒凸点用于低温键合[77]
Figure 25. Copper nanoparticle bumps prepared by magnetron sputtering for low temperature bonding. (a) cross-section SEM image of 20 μm pitch bonding interface; (b) SEM image of a 10 μm copper pad fracture after shear test
图 26 脉冲激光沉积铜纳米颗粒凸点用于低温键合[78]
Figure 26. Copper nanoparticle bumps prepared by PLD for low temperature bonding. (a) Cu nanoparticles bump array prepared by PLD; (b) shear strength at different bonding temperatures ( 15 MPa, 5 min); (c) fracture morphology of bonded Cu bumps (250 ℃,15 MPa, 5 min)
图 27 电镀纳米线工艺流程[82]
Figure 27. Process flow of electroplating nanowires
图 28 不同尺度电镀纳米线焊盘[83]
Figure 28. Different scale plating nanowire pad. (a) nanowire bumps of 5 μm pads with 10 μm pitch; (b) nanowire bumps of 50 μm pads with 100 μm pitch; (c) cross sections of 20 μm contacts; (d) cross sections of 5 μm contact pads
图 29 电镀金属脱合金工艺流程[59]
Figure 29. Electroplating metal and dealloying process. (a) wafer with pads; (b) PVD deposition of diffusion barrier (green) and seed layer (yellow); (c) lithographical priting of photoresist; (d) electroplating of Au socket and Ag/Au depots; (e) photoresist removel and etching of bare plating base; (f) nanoporous bumps prepared by selective dealloying
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[1] Zhang L, Liu Z, Chen S W, et al. Materials, processing and reliability of low temperature bonding in 3D chip stacking[J]. Journal of Alloys and Compounds, 2018, 750: 980 − 995. doi: 10.1016/j.jallcom.2018.04.040
[2] Wiemer M, Haubold M, Jia C, et al. Developments trends in the field of wafer bonding technologies[J]. ECS Transactions, 2008, 16(8): 81. doi: 10.1149/1.2982857
[3] Chen K N, Fan A, Tan C S, et al. Bonding parameters of blanket copper wafer bonding[J]. Journal of Electronic Materials, 2006, 35: 230 − 234. doi: 10.1007/BF02692440
[4] Ko C T, Chen K N. Low temperature bonding technology for 3D integration[J]. Microelectronics reliability, 2012, 52(2): 302 − 311. doi: 10.1016/j.microrel.2011.03.038
[5] 王帅奇, 邹贵生, 刘磊. 先进封装中铜-铜低温键合技术研究进展[J]. 焊接学报, 2022, 43(11): 112 − 125. doi: 10.12073/j.hjxb.20220703003 Wang Shuaiqi, Zou Guisheng, Liu Lei. Research progress of low-temperature Cu-Cu bonding technology for advanced packaging[J]. Transactions of the China Welding Institution, 2022, 43(11): 112 − 125. doi: 10.12073/j.hjxb.20220703003
[6] 黄天, 甘贵生, 刘聪, 等. 电子封装低温互连技术研究进展[J]. 中国有色金属学报, 2023, 33(4): 1144 − 1178. doi: 10.11817/j.ysxb.1004.0609.2021-42856 Huang Tian, Gan Guisheng, Liu Cong, et al. Research progress of low temperature interconnection technology for electronic packaging[J]. The Chinese Journal of Nonferrous Metals, 2023, 33(4): 1144 − 1178. doi: 10.11817/j.ysxb.1004.0609.2021-42856
[7] Hu F, Xu P, Zhang W, et al. A low-temperature solid-state bonding method based on copper bump coated with nickel microcones and silver buffer[J]. Materials Letters, 2016, 181: 165 − 168. doi: 10.1016/j.matlet.2016.06.030
[8] Wang P I, Lee S H, Parker T C, et al. Low temperature wafer bonding by copper nanorod array[J]. Electrochemical and Solid-State Letters, 2009, 12(4): H138. doi: 10.1149/1.3075900
[9] Sakai T, Imaizumi N, Miyajima T. Low temperature Cu-Cu direct bonding for 3D-IC by using fine crystal layer[C]//2012 2nd IEEE CPMT Symposium Japan, IEEE, 2012: 1-4.
[10] Sosa R A, Mohan K, Antoniou A, et al. Low-temperature all-Cu interconnections formed by pressure-less sintering of Cu-pillars with nanoporous-Cu caps[C]//2021 IEEE 71st Electronic Components and Technology Conference (ECTC), IEEE, 2021: 390-394.
[11] Sosa R A, Mohan K, Nguyen L, et al. Cu pillar with nanocopper caps: the next interconnection node beyond traditional Cu pillar[C]//2019 IEEE 69th Electronic Components and Technology Conference (ECTC), IEEE, 2019: 655-660.
[12] Islam N, Pandey V, Kim K O. Fine pitch Cu pillar with bond on lead (BOL) assembly challenges for low cost and high performance flip chip package[C]//2017 IEEE 67th Electronic Components and Technology Conference (ECTC), IEEE, 2017: 102-107.
[13] Lee J B, Aw J L, Rhee M W. 3-D TSV Six-Die Stacking and reliability assessment of 20-μm-pitch bumps on large-scale dies[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2016, 7(1): 33 − 38.
[14] 果世驹. 粉末烧结理论[M]. 北京: 冶金工业出版社, 1998. Guo Shiju. Powder sintering theory[M]. Beijing: Metallurgical Industry Press, 1998.
[15] Fang Z Z, Wang H. Densification and grain growth during sintering of nanosized particles[J]. International Materials Reviews, 2008, 53(6): 326 − 352. doi: 10.1179/174328008X353538
[16] 阮建明, 黄培云. 粉末冶金原理[J]. 北京: 冶金工业出版社, 2012. Ruan Jianming, Huang Peiyun. Principle of powder metallurgy[M]. Beijing: Metallurgical Industry Press, 2012.
[17] Deng Z, Zou G, Zhang H, et al. Bonding Below 150° C Using Nano-Ag Film for Power Electronics Packaging[J]. Journal of Electronic Materials, 2023, 52(6): 3903 − 3913. doi: 10.1007/s11664-023-10358-1
[18] Khiat M N, Wang X, Benabou L, et al. Modeling of the densification of silver particles during sintering at controlled pressure and temperature[J]. Journal of Physics:Conference Series, IOP Publishing, 2018, 1141(1): 012157.
[19] Asoro M A, Kovar D, Shao-Horn Y, et al. Coalescence and sintering of Pt nanoparticles: in situ observation by aberration-corrected HAADF STEM[J]. Nanotechnology, 2009, 21(2): 025701.
[20] Liu Z J, Cheng Q, Wang Y, et al. Sintering neck growth mechanism of Fe nanoparticles: A molecular dynamics simulation[J]. Chemical Engineering Science, 2020, 218: 115583. doi: 10.1016/j.ces.2020.115583
[21] Yan J, Zou G, Liu L, et al. Sintering mechanisms and mechanical properties of joints bonded using silver nanoparticles for electronic packaging applications[J]. Welding in the World, 2015, 59: 427 − 432. doi: 10.1007/s40194-014-0216-x
[22] 郭岩岩, 历长云, 冀国良, 等. 粉末致密化过程数值模拟研究现状[J]. 材料导报, 2022, 36(18): 20080161 − 7. doi: 10.11896/cldb.20080161 Guo Yanyan, Li Changyun, Ji Guoliang, et al. Research status of numerical simulation of powder densification process[J]. Materials Reports, 2022, 36(18): 20080161 − 7. doi: 10.11896/cldb.20080161
[23] Bai J G, Lei T G, Calata J N, et al. Control of nanosilver sintering attained through organic binder burnout[J]. Journal of Materials Research, 2007, 22(12): 3494 − 3500. doi: 10.1557/JMR.2007.0440
[24] Wei W, Gao L, Tan Y, et al. Feasibility investigation and characterization of liquid dispersant–assisted sintering of silver to bond large‐area plates[J]. Advanced Engineering Materials, 2023, 25(10): 2201574. doi: 10.1002/adem.202201574
[25] Grupp R, Nöthe M, Kieback B, et al. Cooperative material transport during the early stage of sintering[J]. Nature Communications, 2011, 2(1): 298. doi: 10.1038/ncomms1300
[26] Wakai F, Okuma G. Rigid body motion of multiple particles in solid-state sintering[J]. Acta Materialia, 2022, 235: 118092. doi: 10.1016/j.actamat.2022.118092
[27] Zuo Y, Zhao C, Robador A, et al. Quasi-in-situ observation of the grain growth and grain boundary movement in sintered Cu nanoparticle interconnects[J]. Acta Materialia, 2022, 236: 118135. doi: 10.1016/j.actamat.2022.118135
[28] Liang P, Pan Z, Tang L, et al. Molecular dynamics simulation of sintering densification of multi-scale silver layer[J]. Materials, 2022, 15(6): 2232. doi: 10.3390/ma15062232
[29] Li S, Liu Y, Ye H, et al. Sintering mechanism of Ag nanoparticle-nanoflake: a molecular dynamics simulation[J]. Journal of Materials Research and Technology, 2022, 16: 640 − 655. doi: 10.1016/j.jmrt.2021.12.029
[30] Zhang Y, Xiao X, Zhang J. Kinetic monte carlo simulation of sintering behavior of additively manufactured stainless steel powder particles using reconstructed microstructures from synchrotron X-ray microtomography[J]. Results in Physics, 2019, 13: 102336. doi: 10.1016/j.rinp.2019.102336
[31] Wang Y U. Computer modeling and simulation of solid-state sintering: A phase field approach[J]. Acta materialia, 2006, 54(4): 953 − 961. doi: 10.1016/j.actamat.2005.10.032
[32] Wakai F, Yoshida M, Shinoda Y, et al. Coarsening and grain growth in sintering of two particles of different sizes[J]. Acta materialia, 2005, 53(5): 1361 − 1371. doi: 10.1016/j.actamat.2004.11.029
[33] Paredes-Goyes B, Jauffres D, Missiaen J M, et al. Grain growth in sintering: A discrete element model on large packings[J]. Acta Materialia, 2021, 218: 117182. doi: 10.1016/j.actamat.2021.117182
[34] Buffat P, Borel J P. Size effect on the melting temperature of gold particles[J]. Physical Review A, 1976, 13(6): 2287. doi: 10.1103/PhysRevA.13.2287
[35] Wang W, Zou G, Jia Q, et al. Mechanical properties and microstructure of low temperature sintered joints using organic-free silver nanostructured film for die attachment of SiC power electronics[J]. Materials Science and Engineering:A, 2020, 793: 139894. doi: 10.1016/j.msea.2020.139894
[36] Guo W, Zhang H, Zhang X, et al. Preparation of nanoparticle and nanowire mixed pastes and their low temperature sintering[J]. Journal of Alloys and Compounds, 2017, 690: 86 − 94. doi: 10.1016/j.jallcom.2016.08.060
[37] Wang C, Li G, Xu L, et al. Low temperature sintered silver nanoflake paste for power device packaging and its anisotropic sintering mechanism[J]. ACS Applied Electronic Materials, 2021, 3(12): 5365 − 5373. doi: 10.1021/acsaelm.1c00857
[38] Oppermann H, Dietrich L. Nanoporous gold bumps for low temperature bonding[J]. Microelectronics Reliability, 2012, 52(2): 356 − 360. doi: 10.1016/j.microrel.2011.06.027
[39] 李俊龙, 徐杨, 赵雪龙, 等. 铜颗粒低温烧结技术的研究进展[J]. 焊接学报, 2022, 43(3): 13 − 24. doi: 10.12073/j.hjxb.20210225002 Li Junlong, Xu Yang, Zhao Xuelong, et al. Research progress of low temperature sintering technology for Cu particles[J]. Transactions of the China Welding Institution, 2022, 43(3): 13 − 24. doi: 10.12073/j.hjxb.20210225002
[40] 杨金龙, 董长城, 骆健. 新型功率模块封装中纳米银低温烧结技术的研究进展[J]. 材料导报, 2019, 33(Z2): 360 − 364. Yang Jinlong, Dong Changcheng, Luo Jian. Development of low temperature sintered nanoscale silver for new power device packaging[J]. Materials Reports, 2019, 33(Z2): 360 − 364.
[41] Yan J. A review of sintering-bonding technology using Ag nanoparticles for electronic packaging[J]. Nanomaterials, 2021, 11(4): 927. doi: 10.3390/nano11040927
[42] Wang M, Mei Y H, Jin J, et al. Pressureless sintered-silver die-attach at 180 °C for power electronics packaging[J]. IEEE Transactions on Power Electronics, 2021, 36(11): 12141 − 12145. doi: 10.1109/TPEL.2021.3074853
[43] Wu Y, Zou G, Wang S, et al. Rapid and low temperature sintering bonding using Cu nanoparticle film for power electronic packaging[J]. Applied Surface Science, 2022, 603: 154422. doi: 10.1016/j.apsusc.2022.154422
[44] Liu J, Chen H, Ji H, et al. Highly conductive Cu–Cu joint formation by low-temperature sintering of formic acid-treated Cu nanoparticles[J]. ACS Applied Materials & Interfaces, 2016, 8(48): 33289 − 33298.
[45] Mou Y, Liu J, Cheng H, et al. Facile preparation of self-reducible Cu nanoparticle paste for low temperature Cu-Cu bonding[J]. Jom, 2019, 71: 3076 − 3083. doi: 10.1007/s11837-019-03517-5
[46] Lee C H, Choi E B, Lee J H. Characterization of novel high-speed die attachment method at 225 °C using submicrometer Ag-coated Cu particles[J]. Scripta Materialia, 2018, 150: 7 − 12. doi: 10.1016/j.scriptamat.2018.02.029
[47] Fang J P, Cai J, Wang Q, et al. Low temperature Au-Au bonding using Ag nanoparticles as intermediate[C]//2020 IEEE 70th Electronic Components and Technology Conference (ECTC), IEEE, 2020: 729-734.
[48] Fang J P, Cai J, Wang Q, et al. Low temperature Au-Au bonding using Ag nanoparticles as intermediate for die attachment in power device packaging[J]. Applied Surface Science, 2022, 593: 153436. doi: 10.1016/j.apsusc.2022.153436
[49] Peng Y, Ye Y, Yu C, et al. Study on the preparation and performance of low-temperature sintering and high-thermal-conductivity silver nanowire film[J]. Metals, 2023, 13(4): 819. doi: 10.3390/met13040819
[50] Yu Z, Tan Y Z, Bayer C F, et al. Cu-Cu thermocompression bonding with Cu-nanowire films for power semiconductor die-attach on DBC substrates[C]//2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC), IEEE, 2021: 1-7.
[51] Strahringer D, Roustaie F, Weissenborn F, et al. Optimizing the nano wiring and KlettSintering parameters for low-temperature die to DCB attach of power electronic chips[C]//2021 16th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), IEEE, 2021: 31-34.
[52] Chen C, Suganuma K. Microstructure and mechanical properties of sintered Ag particles with flake and spherical shape from nano to micro size[J]. Materials & Design, 2019, 162: 311 − 321.
[53] Yeom J, Nagao S, Chen C, et al. Ag particles for sinter bonding: Flakes or spheres[J]. Applied Physics Letters, 2019, 114(25): 253103. doi: 10.1063/1.5099140
[54] Soichi S, Suganuma K. Low-temperature and low-pressure die bonding using thin Ag-flake and Ag-particle pastes for power devices[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2013, 3(6): 923 − 929. doi: 10.1109/TCPMT.2013.2256463
[55] Chen C, Zhang Z, Zhang B, et al. Micron-sized Ag flake particles direct die bonding on electroless Ni–P-finished DBC substrate: low-temperature pressure-free sintering, bonding mechanism and high-temperature aging reliability[J]. Journal of Materials Science:Materials in Electronics, 2020, 31: 1247 − 1256. doi: 10.1007/s10854-019-02636-8
[56] Suganuma K, Sakamoto S, Kagami N, et al. Low-temperature low-pressure die attach with hybrid silver particle paste[J]. Microelectronics Reliability, 2012, 52(2): 375 − 380. doi: 10.1016/j.microrel.2011.07.088
[57] Yang F, Hu B, Peng Y, et al. Ag microflake-reinforced nano-Ag paste with high mechanical reliability for high-temperature applications[J]. Journal of Materials Science:Materials in Electronics, 2019, 30: 5526 − 5535. doi: 10.1007/s10854-019-00846-8
[58] Kim M I, Choi E B, Lee J H. Improved sinter-bonding properties of silver-coated copper flake paste in air by the addition of sub-micrometer silver-coated copper particles[J]. Journal of Materials Research and Technology, 2020, 9(6): 16006 − 16017. doi: 10.1016/j.jmrt.2020.11.069
[59] Dietrich L, Oppermann H, Lopper C, et al. Fabrication and characterization of nanoporous gold (NPG) interconnects for wafer level packaging[C]//2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), IEEE, 2022: 873-882.
[60] Shahane N, Mohan K, Behera R, et al. Novel high-temperature, high-power handling all-Cu interconnections through low-temperature sintering of nanocopper foams[C]//2016 IEEE 66th Electronic Components and Technology Conference (ECTC), IEEE, 2016: 829-836.
[61] Shahane N, Mohan K, Ramos G, et al. Enabling chip-to-substrate all-Cu interconnections: design of engineered bonding interfaces for improved manufacturability and low-temperature bonding[C]//2017 IEEE 67th Electronic Components and Technology Conference (ECTC), IEEE, 2017: 968-975.
[62] Mohan K, Shahane N, Sosa R, et al. Demonstration of patternable all-Cu compliant interconnections with enhanced manufacturability in chip-to-substrate applications[C]//2018 IEEE 68th Electronic Components and Technology Conference (ECTC), IEEE, 2018: 301-307.
[63] Hyun W J, Secor E B, Hersam M C, et al. High-resolution patterning of graphene by screen printing with a silicon stencil for highly flexible printed electronics[J]. Advanced Materials, 2015, 27(1): 109 − 115. doi: 10.1002/adma.201404133
[64] Liang J, Tong K, Pei Q. A water-based silver-nanowire screen-print ink for the fabrication of stretchable conductors and wearable thin‐film transistors[J]. Advanced Materials, 2016, 28(28): 5986 − 5996. doi: 10.1002/adma.201600772
[65] Li J, Rossignol F, Macdonald J. Inkjet printing for biosensor fabrication: combining chemistry and technology for advanced manufacturing[J]. Lab on a Chip, 2015, 15(12): 2538 − 2558. doi: 10.1039/C5LC00235D
[66] Yang P, Zhang L, Kang D J, et al. High-resolution inkjet printing of quantum dot light-emitting microdiode arrays[J]. Advanced Optical Materials, 2020, 8(1): 1901429. doi: 10.1002/adom.201901429
[67] Park J U, Lee S, Unarunotai S, et al. Nanoscale, electrified liquid jets for high-resolution printing of charge[J]. Nano Letters, 2010, 10(2): 584 − 591. doi: 10.1021/nl903495f
[68] Mishra S, Barton K L, Alleyne A G, et al. High-speed and drop-on-demand printing with a pulsed electrohydrodynamic jet[J]. Journal of Micromechanics and Microengineering, 2010, 20(9): 095026. doi: 10.1088/0960-1317/20/9/095026
[69] Wang D, Wang Q, Meng Q, et al. High temperature-assisted electrohydrodynamic jet printing of sintered type nano silver ink on a heated substrate[J]. Journal of Micromechanics and Microengineering, 2019, 29(4): 045012. doi: 10.1088/1361-6439/ab0739
[70] Zürcher J, Yu K, Schlottig G, et al. Nanoparticle assembly and sintering towards all-copper flip chip interconnects[C]//2015 IEEE 65th Electronic Components and Technology Conference (ECTC), IEEE, 2015: 1115-1121.
[71] Del Carro L, Zürcher J, Drechsler U, et al. Low-temperature dip-based all-copper interconnects formed by pressure-assisted sintering of copper nanoparticles[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2019, 9(8): 1613 − 1622. doi: 10.1109/TCPMT.2019.2891111
[72] Del Carro L. Sintering of copper nanoparticle pastes for microelectronic packaging[D]. ETH Zurich, 2018.
[73] Del Carro L, Kossatz M, Schnackenberg L, et al. Laser sintering of dip-based all-copper interconnects[C]//2018 IEEE 68th Electronic Components and Technology Conference (ECTC), IEEE, 2018: 279-286.
[74] Zürcher J, Del Carro L, Schlottig G, et al. All-copper flip chip interconnects by pressureless and low temperature nanoparticle sintering[C]//2016 IEEE 66th Electronic Components and Technology Conference (ECTC), IEEE, 2016: 343-349.
[75] 吴永超, 胡锦涛, 郭伟, 等. 微米银焊点的超快激光图形化沉积及其在芯片连接中的应用探索[J]. 中国激光, 2022, 49(2): 0202002. doi: 10.3788/CJL202249.0202002 Wu Yongchao, Hu Jintao, Guo Wei, et al. Ultrafast laser patterning deposition of micron sliver bumps for chip bonding application[J]. Chinese Journal of Lasers, 2022, 49(2): 0202002. doi: 10.3788/CJL202249.0202002
[76] 吴永超, 王帅奇, 郭伟, 等. 纳米银微焊点阵列的超快激光图形化沉积及其芯片封装研究[J]. 机械工程学报, 2022, 58(2): 166 − 175. doi: 10.3901/JME.2022.02.166 Wu Yongchao, Wang Shuaiqi, Guo Wei, et al. Patterning deposition of nano-sliver micro bumps array by ultrafast laser and its chip packaging research[J]. Journal of Mechanical Engineering, 2022, 58(2): 166 − 175. doi: 10.3901/JME.2022.02.166
[77] Wu Z, Wang Q, Song C, et al. Low temperature fine-pitch wafer-level Cu-Cu bonding using nanoparticles fabricated by PVD[C]//2018 IEEE 68th Electronic Components and Technology Conference (ECTC), IEEE, 2018: 287-292.
[78] Wang S, Zou G, Wu Y, et al. Patterned Cu nanoparticle film for All-Cu interconnection without chemical mechanical polishing pretreatment[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2023, 13(5): 604 − 614. doi: 10.1109/TCPMT.2023.3278320
[79] Lee S A, Yang J W, Choi S, et al. Nanoscale electrodeposition: Dimension control and 3D conformality[J]. Exploration, 2021, 1(3): 20210012. doi: 10.1002/EXP.20210012
[80] Roustaie F, Quednau S, Dassinger F, et al. In-situ synthesis of metallic nanowire arrays for ionization gauge electron sources[J]. Journal of Vacuum Science & Technology B, 2016, 34(2): 02G103.
[81] Roustaie F, Bieker J, Cicek R, et al. Novel fabrication method for integration of template grown metallic nanocones with controllable tip diameter and apex angle[J]. Microelectronic Engineering, 2017, 180: 81 − 85. doi: 10.1016/j.mee.2017.06.003
[82] Roustaie F, Quednau S, Weissenborn F, et al. Room temperature KlettWelding interconnect technology for high performance CMOS logic[C]//2021 IEEE 71st Electronic Components and Technology Conference (ECTC), IEEE, 2021: 371-376.
[83] Roustaie F, Quednau S, Dassinger F, et al. Room temperature interconnection technology for bonding fine pitch bumps using NanoWiring, KlettWelding, KlettSintering and KlettGlueing[C]//2020 15th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), IEEE, 2020: 168-171.
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