Research progress of low-temperature Cu-Cu bonding technology for advanced packaging
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摘要: Cu-Cu低温键合技术是先进封装的核心技术，相较于目前主流应用的Sn基软钎焊工艺，其互连节距更窄、导电导热能力更强、可靠性更优. 文中对应用于先进封装领域的Cu-Cu低温键合技术进行了综述，首先从工艺流程、连接机理、性能表征等方面较系统地总结了热压工艺、混合键合工艺实现Cu-Cu低温键合的研究进展与存在问题，进一步地阐述了新型纳米材料烧结工艺在实现低温连接、降低工艺要求方面的优越性，概述了纳米线、纳米多孔骨架、纳米颗粒初步实现可图形化的Cu-Cu低温键合基本原理. 结果表明，基于纳米材料烧结连接的基本原理，继续开发出宽工艺冗余、窄节距图形化、优良互连性能的Cu-Cu低温键合技术是未来先进封装的重要发展方向之一.Abstract: Low-temperature Cu-Cu bonding technology is the core technology for advanced packaging. Compared with the mainstream Sn-based soldering process, it can achieve finer pitch, higher electrical and thermal conductivity. In this paper, low-temperature Cu-Cu bonding technology for advanced packaging is reviewed. The research progress of low-temperature Cu-Cu bonding realized by thermal compression bonding and hybrid bonding is systematically summarized from the aspects of process flow, bonding mechanism and performance characterization. The advantages of the newly-developed nanomaterial sintering process in reducing bonding temperature and process requirements are further expounded. Mechanism of patterned nanowires, nano-porous frameworks and nanoparticles for low-temperature bonding are summarized. Low-temperature Cu-Cu bonding technology for advanced packaging are forecast.
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Keywords:
- advanced packaging /
- hybrid bonding /
- Cu-Cu bonding /
- fine pitch /
- sintering
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图 1 由(111) 取向的纳米孪晶Cu凸点实现Cu-Cu键合[15-17]
Figure 1. Cu-Cu bonding enabled by (111)-oriented nanotwinned Cu bumps. (a) The microbump cross-section analyzed by FIB; (b) surface orientation of an nt-Cu microbump observed by EBSD; (c) cross-sectional FIB ion-image of a Cu joint bonded at 300 ℃/93 MPa/10 s; (d) cross-sectional FIB ion-image for post-annealed sample
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图 2 飞行切割[19]
Figure 2. Fly-cutting. (a) schematic illustration of fly-cutting; (b) optical images of cut Cu bumps surface
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图 3 飞行切割细化表面晶粒[20]
Figure 3. Fly-cutting process introduces finer grains. (a) SEM image of initial Cu surface; (b) EBSD image of initial Cu surface; (c) SEM image of cut Cu surface; (d) EBSD image of cut Cu surface
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图 5 键合后的SEM图像[22]
Figure 5. SEM cross-sectional view of Cu-Cu bonding. (a) with bonding condition of 150 ℃, 1 min, 500 MPa; (b) bottom bonding interface; (c) sidewall bonding interface
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图 8 Ti作钝化层的键合结果[26]
Figure 8. Ti passivation bonded results. (a) SEM image; (b) TEM image
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图 9 自组装分子层钝化方法的原理和工艺流程[31]
Figure 9. Schematic illustration and process flow of self-assembled monolayer method. (a) before bonding; (b) after bonding
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图 10 Cu-Cu键合界面的TEM图像[32]
Figure 10. TEM micrographs of bonded Cu layers. (a) without SAM passivation; (b) with SAM passivation
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图 14 Si作为SiO2-SiO2室温键合的中间层[44]
Figure 14. Bonding of SiO2 and SiO2 at room temperature using Si ultrathin film
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图 15 基于SAB的混合键合流程示意图[46]
Figure 15. Process flow of the combined SAB with (a) UHV bonding and (b) hydrophilic bonding
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图 17 Cu和粘结剂混合键合方式[50]
Figure 17. Cu/adhesive hybrid bonding. (a) “adhesive-first” hybrid bonding process; (b) “Cu-first” hybrid bonding process
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图 19 键合前后的Cu纳米线[56]
Figure 19. Cu nanowires before and after bonding. (a) entire wafer covered with Cu nanowires; (b) 5 μm pads with 10 μm pitch; (c) cross sections of about 60 μm and; (d) 10 μm pitch connected with nanowires
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图 20 Cu纳米多孔骨架的图形化路线[62]
Figure 20. Process flow for fabrication of patterned np-Cu foam films
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图 21 纳米多孔骨架的组织形态[62]
Figure 21. Morphology of dealloyed np-Cu foam film. (a) low magnification; (b) high magnification
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图 22 250 ℃/9 MPa/30 min烧结条件下的键合界面[62]
Figure 22. Cross-sectional images of the sintered joint under the condition of 250 ℃/9 MPa/30 min
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图 23 不同互连技术的示意图[67]
Figure 23. Schematic of different packaging technology. (a) advanced packaging technology; (b) power device packaging technology
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图 24 浸蘸转移法进行焊膏图形化[68]
Figure 24. Process sequence of the dipping method. (a) preparation of a Cu ink film; (b) dip into Cu ink film by Cu pillar chip; (c) ink transfer and alignment to substrate; (d) joint formed by nanoparticle sintering
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图 25 键合压力对接头组织和剪切强度的影响[71]
Figure 25. Effects of bonding pressure on microstructures and interconnect resistance. (a) microstructures; (b) interconnect resistance
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